1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a gate dielectric formed between a gate conductor and a channel region of a transistor. An interfacial region of the gate dielectric in close proximity to the channel region is incorporated with nitrogen atoms using gas cluster ion beam implantation to make the interfacial region resistant to penetration by foreign species.
2. Description of the Related Art
Fabrication of metal-oxide-semiconductor ("MOS") transistors is well-known. The manufacturing process begins by lightly doping a single crystalline silicon substrate with n-type or p-type species. Active areas of the substrate in which the transistors and other active devices will reside are then isolated from other active areas with isolation structures. Isolation structures may comprise shallow trenches in the substrate which are filled with a dielectric. Isolation structures may alternatively comprise local oxidation of silicon ("LOCOS") structures. A gate oxide (i.e., silicon dioxide) is then formed upon the substrate by thermally oxidizing the silicon-based substrate. A gate conductor is formed by depositing polycrystalline silicon ("polysilicon") upon the gate dielectric, followed by patterning the polysilicon using typical masking and etching techniques. Subsequently, the polysilicon gate conductor and source/drain regions arranged within the substrate on opposite sides of the gate conductor are concurrently doped with a high dosage of n-type or p-type dopants. If the impurity dopant is n-type, then the resulting transistor is referred to as an NMOS device. Conversely, if the impurity dopant is p-type, then the resulting transistor is referred to as a PMOS device. An integrated circuit which employs both NMOS and PMOS devices is generally known as a complementary MOS or CMOS circuit
The resistivity of the polysilicon gate conductor is reduced by the introduction of impurities into the structure. Enough dopants are introduced so that the sheet resistance of the gate conductor is reduced to, in some instances, less than approximately 500 ohms/sq. In an ion implantation process, the depth at which the dopants are implanted can be controlled by adjusting the energy provided to the ions by the ion implantation equipment. However, the minimum depth of implantation is limited to between 200 .ANG. and 400 .ANG. because the energy of each ion is typically too large to permit a lesser depth of implantation.
Subsequent processing steps may require heating of the semiconductor topography. For example, a post-implant anneal is often performed to position and activate the dopants implanted into the source/drain regions and the gate conductor. Dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate than dopants with a low diffusivity. For instance, boron which is commonly used to dope the polysilicon gate and the source/drain regions of an NMOS device undergoes fast diffusion. On the other hand, arsenic which is typically used to dope the polysilicon gate and the source/drain regions of a PMOS device is a slow diffuser. Unfortunately, dopants, like boron, which readily migrate during heat treatment may diffuse from the gate conductor through the gate oxide and into the channel region of the transistor. Boron penetration into the channel can lead to undesirable effects, such as an increase in electron trapping, a decrease in low-field hole mobility, degradation of the transistor drive current, and increased subthreshold current.
Transistor operation may also be detrimentally affected by hot carrier injection ("HCI") into the gate dielectric. HCI is a phenomena by which the kinetic energy of the charge carriers (holes or electrons) is increased as they are accelerated through large potential gradients, causing the carriers to become "hot". The greatest potential gradient, often referred to as the maximum electric field ("Em") occurs near the drain during saturated operation. The hot carriers may become injected into and trapped within the gate dielectric. Traps within the gate dielectric generally become electron traps, even if they are initially filled with holes. As a result of trapped charge accumulating over time in the gate dielectric, an undesirable shift in the threshold voltage of the transistor may occur.
In an attempt to prevent the diffusion of impurities into the channel region and the injection of hot carriers into the gate oxide, barrier atoms are commonly incorporated into the gate oxide/channel interfacial region. For example, nitrogen is commonly introduced into the interfacial region by annealing the semiconductor topography in an ambient comprising N.sub.2. Available N atoms may react with Si atoms and O atoms of the gate oxide to form silicon oxynitride ("oxynitride"), terminating any dangling bonds within the gate oxide. The presence of strong N--O bonds of oxynitride throughout the gate oxide would serve to reduce the entrapment of hot carriers within the gate oxide. That is, the hot carriers would have no dangling bonds with which to bond. Further, single N atoms would block the migration pathways into and through the gate oxide, inhibiting fast diffusing impurities from passing from the gate conductor into the channel region. The single N atoms would also form a barrier at the gate oxide/channel interface, inhibiting the injection of hot carriers into the gate oxide.
Unfortunately, only a small fraction (e.g., 1/1000) of the N.sub.2 molecules actually break up into separate N atoms upon entering the gate oxide. As such, only a few N atoms are free to react with dangling bonds within the gate oxide. Further, it is believed that the N.sub.2 molecules, unlike individual N atoms, may be too large to fill interstitial positions and vacancies within the gate oxide. Consequently little if any protection against hot carrier injection into, and impurity diffusion through, the gate oxide is accomplished by the N.sub.2 diffusion process.
Ion implantation of barrier atoms, e.g., N atoms, into the gate oxide/channel interfacial region has also been employed to prevent species from passing into and out of the gate oxide. The gate oxide may be less than 50 .ANG. thick to ensure high capacitive coupling between the channel and the gate conductor. Ion implantation involves accelerating the ions in an electric field to increase the energy of each ion to greater than 10 keV. Absent the ability to achieve lower energies for the ions, the ions are implanted into a medium to a minimum depth of between 200 and 400 .ANG.. Accordingly, atoms implanted into the gate oxide may migrate well-below the gate oxide/channel interface. The atoms thusly placed fill no interstitial and vacancy positions within the gate oxide. Therefore, the atoms provide no barrier to the migration of impurities from the gate conductor into the channel and to the injection of hot carriers into the gate oxide. The gate oxide, absent of the barrier atoms, still containg dangling bonds, and hence hot carrier traps. Consequently, the implanted barrier atoms do not provide adequate protection against the entrapment of hot carriers escaping into the gate oxide.
It would therefore be of benefit to develop a method for forming a diffusion barrier between the gate conductor and the channel region of a transistor to prevent the migration of dopants into the channel region. It would also be desirable to reduce charge carrier injection into and entrapment within the gate dielectric. Accordingly, dangling bonds within the gate dielectric must be eliminated, and the diffusion barrier must be placed at the gate dielectric/channel interfacial region. Ion implantation of barrier atoms using conventional methods should be avoided to ensure that the diffusion barrier is accurately positioned in the gate dielectric/channel interfacial region. Otherwise, the barrier atoms might be implanted beneath the interfacial region where they would provide little protection against hot carrier injection into the gate dielectric and dopant diffusion into the channel. In addition, barrier atoms provided to the gate dielectric/channel interfacial region must be free to bond with dangling bonds and fill voids within the gate dielectric.